The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a transistor comprising a gate structure, by which method a patterned layer is applied defining the area of the gate structure, and a dielectric layer is applied in such a way, that the thickness of the dielectric layer next to the patterned layer is substantially equally large or larger than the height of the patterned layer, which dielectric layer is removed over part of its thickness until the patterned layer is exposed, after which the patterned layer is subjected to a material removing treatment, thereby forming a recess in the dielectric layer, and a conductive layer is applied filling the recess, which conductive layer is shaped into the gate structure.
Such a method is known from U.S. Pat. No. 5,856,225. This method is often referred to as replacement gate technique. In order to subsequently make electrical contact with the surface of the semiconductor body, conventional CMOS process flow steps need to be carried out, that is to say a contact window needs to be etched in the dielectric layer at the area of the planned electrical contact, which contact window needs to be filled by applying a further conductive layer, which further conductive layer needs to be shaped locally into a contact structure establishing the electrical contact with the surface of the semiconductor body.
A disadvantage of this method is that an additional conductive layer is required for the provision of an additional interconnect layer comprising the contact structure establishing the electrical contact with the surface of the semiconductor body. A further disadvantage is that after planarisation of the dielectric layer, a contact to the gate structure is to be made in the same process step as a contact to the semiconductor body, which latter contact requires etching and subsequent metal filling to a larger depth than the former contact.
It is an object inter alia of the invention to provide a method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph, which method enables the provision of an additional interconnect layer without increasing the number of metal deposition steps.
Another object of the invention is to provide a method, which enables the provision of a contact to the gate structure and a contact to the semiconductor body in the same process step, which latter contact requires etching and subsequent metal filling to a similar depth as the former contact.
According to the invention, this object is achieved in that, prior to the application of the conductive layer, a contact window is provided in the dielectric layer, which contact window is filled with the conductive layer, which conductive layer is locally shaped into a contact structure establishing electrical contact with the surface of the semiconductor body.
As the gate structure and an additional interconnect layer comprising the contact structure are provided from a single conductive layer, no additional metal deposition step is needed.
Although only part of the patterned layer may be removed during the material removing treatment and replaced by the conductive layer, it is advantageous to remove the patterned layer completely during this treatment and apply an insulating layer in the recess thus formed at the area of the gate structure, which insulating layer forms a gate dielectric of the transistor. In this way, the flexibility as regards the choice of materials for the gate structure and the gate dielectric is increased. In order to improve the performance of the transistor, it may be advantageous to apply a dielectric material with a dielectric constant higher than that of silicon oxide (xcex5xcx9c4) as the gate dielectric and, hence, as the insulating layer from which the gate dielectric is formed. In this respect, tantalum oxide (Ta2O5; xcex5xcx9c20-25), aluminum oxide (Al2O3; xcex5xcx9c10) or silicon nitride (Si3N4; xcex5xcx9c7) can be applied to advantage, as these materials are deposited in a conformal and reproducible way by means of chemical vapor deposition (CVD). The conductive layer, from which the gate structure of the transistor and the contact structure are formed, is advantageously applied by depositing a layer comprising a metal or a combination of metals. In contrast with polycrystalline silicon, which is often applied as a gate material, metals intrinsically have a relatively low resistance and do not suffer from detrimental depletion effects. In this respect, a low-resistance metal such as aluminum, tungsten, copper or molybdenum can be advantageously applied. If a metal or a combination of metals is used, the conductive layer is preferably applied as a double-layer consisting of a layer composed of the metal or the combination of metals on top of a layer acting as adhesion layer, barrier layer, or adhesion layer and barrier layer. In this respect, titanium (Ti) or tantalum (Ta) may be applied as adhesion layer and titanium nitride (TiN), tantalum nitride (TaN) or titanium tungsten (TiW) as barrier layer.
In order to increase the compactness of the semiconductor device, the conductive layer, which fills the recess at the area of the gate structure and the contact window at the area of the contact structure, is advantageously subjected to a maskless material removing treatment until the conductive layer overlying the dielectric layer is removed. In this way the gate structure and the contact structure are fully recessed in the dielectric layer, which is characteristic of a damascene process. The above mentioned maskless removal of the conductive layer is preferably accomplished by means of chemical-mechanical polishing (CMP). A subsequent maskless removal of the insulating layer is not required, but can be beneficial if the insulating layer involves a high dielectric constant material.
In order to suppress e.g. short-channel effects such as punch-though and short-channel threshold-voltage reduction, which effects start to play an important role in the device behavior of MOS transistors with channel lengths decreasing below 2 xcexcm, impurities can be advantageously introduced via the recess at the area of the gate structure into the semiconductor body in a self-registered way by using the dielectric layer as a mask. The impurities are advantageously introduced into the semiconductor body by means of ion implantation, which in general includes a high-temperature anneal, which is used to restore the damage in the crystal lattice caused by the implantation and to activate the as-implanted impurities.
In order to further increase the compactness of the semiconductor device, the contact structure is advantageously applied covering at least part of an oxide field insulating region, which is provided at the surface of the semiconductor body to separate active regions in the semiconductor body. Such a contact structure is also referred to as a borderless contact In certain circumstances it may be advantageous that the contact structure establishes an electrical contact between active regions separated from each other by an oxide field insulating region. In case of a CMOS inverter, an electrical contact needs to be established between the drain of an NMOS transistor and the drain of an adjacent PMOS transistor.
The contact window may be provided in the dielectric layer by locally etching this layer on the basis of a fixed time or using end-point detection. However, in order to counteract serious etching of the underlying oxide field insulating region, the surface of the semiconductor body at the area of the contact structure is advantageously provided with an etch stop layer prior to the application of the dielectric layer, which etch stop layer is composed of a material with respect to which the dielectric layer is selectively etchable. In this respect, it is advantageous to apply silicon nitride as the etch stop layer and silicon oxide as the dielectric layer. Alternatively, aluminum oxide can be used instead of silicon nitride and/or PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass) instead of silicon oxide.
The patterned layer defining the area of the gate structure of the transistor may be applied composed of, for example, silicon nitride or aluminum oxide. However, in order to match the process flow to conventional CMOS processing, the patterned layer is advantageously applied comprising a semiconductor material.
The patterned layer may be advantageously applied by depositing and patterning a layer comprising a silicon germanium alloy. The layer may be composed of a silicon germanium alloy, which is given by the chemical formula GexSi(1xe2x88x92x), or a silicon germanium alloy with a small percentage of carbon, which is given by the chemical formula GexSi(1xe2x88x92xxe2x88x92y)Cy. In these formulas x represents the fraction of germanium lying in the range between about 0.1 and 1, y the fraction of carbon lying in the range between about 0.001 and 0.05, and (1xe2x88x92x) respectively (1xe2x88x92xxe2x88x92y) the fraction of silicon. When subjected to a wet chemical etching treatment in e.g. a hot, concentrated sulphuric acid (H2SO4) solution, such a silicon germanium alloy etches about 10 times or more faster than silicon.
One embodiment of the method in accordance with the invention, in which silicon is advantageously used as the semiconductor material, is characterized in that the patterned layer is applied by depositing and patterning a layer comprising silicon, and the dielectric layer is applied, after which the patterned layer is subjected to the material removing treatment wherein the silicon of the patterned layer is etched away, thereby forming the recess at the area of the gate structure, after which the dielectric layer is provided with the contact window at the area of the contact structure.
Another embodiment of the method in accordance with the invention, in which silicon is advantageously used as the semiconductor material, is characterized in that, prior to the application of the patterned layer, a masking layer is applied to the surface of the semiconductor body, which semiconductor body is a silicon body, the masking layer being composed of a material with respect to which silicon is selectively etchable, after which the patterned layer is applied by depositing and patterning a layer comprising silicon, and the dielectric layer is applied, which dielectric layer is provided with the contact window at the area of the contact structure, which contact window exposes the masking layer, after which the patterned layer is subjected to the material removing treatment wherein the silicon of the patterned layer is etched away, thereby forming the recess at the area of the gate structure. The masking layer is applied in order to protect the surface of the silicon body at the area of the contact structure from being attacked by the etching mixture applied for etching of the silicon present in the patterned layer. In this respect, silicon oxide may, for example, be advantageously applied as the masking layer, although other materials may also be used.
The dielectric layer is advantageously removed over part of its thickness by means of chemical-mechanical polishing. Experimentally, it is observed that the moment of stopping the chemical-mechanical polishing (CMP) of the dielectric layer is rather critical if the patterned layer comprises semiconductor material. If the CMP process is stopped too early, remainders of the dielectric layer are left on the patterned layer which hinder the subsequent removal of the patterned layer or part of the patterned layer. If the CMP process is carried on too long, the definition of the height of the planned gate structure is adversely affected. In order to improve the height definition of the process, it is advantageous to apply the patterned layer as a double-layer with a first sub-layer comprising the semiconductor material with on top a second sub-layer composed of a material having a larger resistance towards the removal of the dielectric layer than the semiconductor material and being selectively etchable with respect to the dielectric layer. Hence, the second sub-layer will act as etch stop layer during the removal of the dielectric layer. In this respect, it is advantageous to apply silicon nitride as the second sub-layer and silicon oxide as the dielectric layer. Alternatively, aluminum oxide can be used instead of silicon nitride and/or PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass) instead of silicon oxide.
After shaping the conductive layer into the gate structure and the contact structure, a further dielectric layer is applied, in which further dielectric layer vias are etched exposing at least part of the gate structure and at least part of the contact structure, which vias are filled by applying a further conductive layer. By using the method in accordance with the invention, the vias exposing the gate structure and the contact structure are of a similar depth, which facilitates etching and conformal filling of these vias.